Venue: AB 10/103
Time: L1, K1, E1, E2

  • Monday, Tuesday: 15:30 – 16:50
  • Wednesday, Friday: 10:00 – 11:20

Semester: Classes commence Week 1 (week of 4 Aug 2026); last day of classes Week 15 (week of 16 Nov 2026 / last day 19 Nov 2026)

This is the course website for ES-204 Digital Systems. It covers student-facing policies and the week-by-week plan. Deadlines are given week-by-week; exact calendar dates will be added later.

Course content (CAT-SOOP): Introduction to Digital Electronics · Modules. Google Classroom link TBD.

General Information

Role Name Contact
Instructor Manu Awasthi Use staff alias below
Head TA NJ Vinay Chandra Use staff alias below
Head TA Neal Apte Use staff alias below
Additional TAs TBD Use staff alias below

Teams: Students work in groups of 2 or 3. Exact team size will be fixed once enrollment is confirmed (~200 students expected).

Kits: Every team receives a component kit (breadboards, wires, ICs, LEDs, DIP switches, etc.). Most contact time is spent building, not listening to lectures.

Contacting Course Staff

The only method for contacting course staff is through the course staff email alias (es204-staff@googlegroups.com). We will filter course email through this alias. Any personal emails to the instructor or the TAs will not be entertained.

Use the Google Classroom discussion or help channel for questions that may benefit the whole class. Email-based questions will only be entertained for policy-related clarifications.

Learning Management System

We use two platforms:

Platform Role
CAT-SOOP Course content (modules, exercises, projects). Already hosted on the Madhava CAT-SOOP instance.
Google Classroom Announcements, class organization, discussion/help, and submissions as announced. Classroom link / join code TBD.
  • All announcements for the class will be made via Google Classroom. Make sure you sign up for the Classroom page.
  • Work through day-to-day material on CAT-SOOP: course home and modules.
  • Policies, schedule, and other course material will also be linked from this page and/or posted on Google Classroom.
  • Student submissions (videos, reflections, project uploads) are accepted only through CAT-SOOP and/or Google Classroom, as specified for each assignment. No email submissions will be considered.

Office Hours

Who When / Where
Instructor After class / TBD
Head TAs (NJ Vinay Chandra, Neal Apte) TBD
Section TAs TBD

Course Philosophy

This is a hands-on course. Lecturing is kept to a minimum: roughly 30–40 minutes per week across the contact slots. The remaining contact time is for building, debugging, and milestone demos.

Every concept is applied on the breadboard. When a circuit does not work (and often it will not at first), troubleshooting is part of the learning. Projects must actually work.

Modules and exercises follow the CCL / Madhava Digital Electronics sequence: prerequisites → counters and clocks → sequential logic → combinational design → arithmetic → advanced arithmetic → signed calculator capstone.

Class Policies

The following is a tentative guideline and may change. Changes will be announced on Google Classroom and reflected here.

Grading (tentative)

Component Weight Nature
Projects 70% Team
Reflections 15% Individual
Final exam 15% Individual

Projects (70%) — working hardware + proof of work

Suggested internal split (sums to 70%; may be adjusted):

Deliverable Weight
Project 1 — Digital Clock 10%
Project 2 — Up/Down Counter 10%
Project 3 — Binary to 7-segment Decoder 10%
Project 4 — 4-bit Calculator 10%
Project 5 — Signed Calculator 10%
Capstone 20%

Projects are graded primarily on whether the circuit works as specified, plus the required proof-of-work video. Partial credit is possible for clearly demonstrated, testable submodules when the full system is incomplete; rubrics will be posted per project.

Reflections (15%) — individual

  • One reflection per module (Modules 0–6 / Capstone).
  • The format is released toward the end of each module.
  • Equal weight across reflections unless otherwise announced.
  • Reflections are individual work even when the build is done in a team.

Final exam (15%) — individual

  • One end-of-term exam during the Examination II window (20–28 Nov 2026).
  • Format TBD (written + practical).

There is no mid-term exam for this course. Examination I week is treated as a light buffer for project work (see schedule).

Presence and milestone demos (no roll call)

There is no mandatory attendance percentage and no attendance sheets. You decide whether to sit through the short lecture segments. Contact hours exist so you can build with staff present and complete milestone demos.

Credit attaches to demonstrated progress, not to being seated in the room. The instructors and TAs may ask for progress checks from individual teams during any of the contact hours.

Weekly milestone demos

  • Each week has a milestone (see Week-by-Week Schedule at the bottom of this page).
  • During contact hours, teams complete a short live check-in (about 30–60 seconds): show the working circuit for that week’s milestone.
  • In addition, you will also be required to upload a working video submission for every milestone. Only one video submission needs to be done from every team, along with a short write-up of the contribution of each team member. Each member is expected to write the contributions of the other team member(s).

Soft enforcement (not roll call)

  • Miss two consecutive milestone demos without an approved makeup → the project grade for the active module is capped at 70% until a makeup demo is completed with staff.
  • Chronic non-engagement (repeated missed demos and missing submissions) will be escalated to course staff review and may affect eligibility for full project credit.
  • Skipping the lab block means you lose the easy path to milestone credit; that is by design for a kit-based course.

The instructor and TAs may cold-call students present in the room during short discussion segments. You need not be correct; you are expected to attempt an answer.

Submission and late policies

Start early. Starting a project on the day of the deadline historically leads to weak builds and creates conditions that encourage plagiarism—avoid both.

  • Deadlines are stated as end of Week N (exact clock time TBD when calendar dates are published).
  • Late submissions are counted at day granularity. If the deadline is 23:59 and you submit at 00:02, that is one day late.
  • For every extra day late: −25% of the assignment’s value. At −100%, the submission is not graded.
  • Emails requesting extensions automatically cost −5% of the points earned on that submission, and the request will be denied except for genuine medical emergencies. Consider extension requests carefully before contacting staff.

Academic integrity and plagiarism

Inspired by prior course practice (CS 1216 policies): this course has zero tolerance for cheating and plagiarism.

What is allowed

  • Full collaboration within your team on builds, debugging, and project videos.
  • Discussion of concepts with other teams (ideas, datasheet reading tips, high-level approaches).

What is not allowed

  • Copying another team’s schematics, wiring layouts, photos, videos, or reflection text.
  • Submitting work you cannot explain.
  • Having someone else build your circuit, or presenting another team’s kit as yours.
  • Using generative tools or web sources to produce reflection text that you present as your own without attribution where required by the reflection prompt.

Disclosure

  • Reflections include a field for collaborators / discussants outside your team. List them. If you are unsure whether something counts as plagiarism, ask staff before submitting. “I didn’t know that counted” is not an accepted excuse.

Proof of work

  • Project videos must show your team’s own kit and a brief narration identifying team members.
  • Staff may spot-viva any team on a submitted circuit. Inability to explain your own build is treated as an integrity red flag and may trigger investigation.

Consequences

Any evidence of academic integrity violation in projects, videos, reflections, or the exam will result in an F grade for the entire course, no exceptions, and a report under institute academic integrity procedures.

Teams, free-riding, and group changes

  • Teams form by the deadline announced in Week 1 (default: end of Week 1).
  • If a teammate is not contributing, flag it early to a head TA. Process: peer flag → staff mediation → possible grade split or team restructuring.
  • Do not wait until the final project video to report free-riding.

Device use during contact hours

Screens are discouraged during the short lecture segments unless explicitly permitted for the activity. During lab/build time, laptops/phones may be used for datasheets, module pages, and documentation. If device use disrupts others, you will be asked to put it away or leave the session.

Kits and Lab Norms

Kit contents (typical)

Breadboards, jumper wires, logic ICs, LEDs, resistors, DIP switches, 7-segment displays, buttons, and related passive components as issued. Exact inventory list TBD at kit distribution.

Checkout and responsibility

  • Kits are issued per team. All members share responsibility for the kit.
  • Keep an inventory checklist. Report missing or damaged parts to TAs promptly.
  • Damage / loss: replacement policy TBD (may include charge for negligent loss). Do not cannibalize another team’s kit.
  • Return kits as instructed at end of term (TBD).

Safety and good practice

  • Confirm power polarity and voltage before connecting ICs.
  • Orient ICs correctly (notch / pin 1); never hot-plug under power if avoidable.
  • Use appropriate series resistors with LEDs.
  • Power down before major rewiring.
  • No food or drink on the workbench near open kits.

Video submissions

  • Typical project video: up to ~60 seconds unless a project specifies otherwise (capstone may allow slightly longer if announced).
  • Show inputs, outputs, and that the circuit behaves correctly for the required cases.
  • Upload only via CAT-SOOP and/or Google Classroom, as specified for that assignment. Videos are used for grading; do not post course videos publicly unless permitted.
  • Privacy: only enrolled teammates need appear; no requirement to film other students.

Modules

Day-to-day exercises and projects are on CAT-SOOP — open these links and work through the material directly:

Week-by-Week Schedule

Shared pace: everyone starts in Week 1 (week of 4 Aug 2026). Second-year cohort; one schedule.

Important calendar notes:

  • Examination I: 18–23 Sep 2026 — no new project deadlines that week
  • Mid-semester recess: 17–25 Oct 2026 — no classes; no deadlines during recess
  • Last day of classes: 19 Nov 2026
  • Examination II (final exam): 20–28 Nov 2026

Each week: short lecture (part of the 30–40 min/week budget) + lab/build time + milestone demo window.

Week Approx. dates Focus Team milestone (end of week) Individual
1 4–8 Aug Kickoff, policies, kits, Module 0 Kit received; Prereq (DIP ↔ 7-seg) demo Team formation
2 10–15 Aug Module 1: Boolean + number reps Ex 1.1–1.2 working —
3 17–22 Aug Module 1: Counters + reset Ex 1.3–1.4 working —
4 24–29 Aug Project 1: Digital Clock P1 demo + video Reflection M1
5 31 Aug–5 Sep Module 2: Debounce, latches, FFs Ex 2.0–2.2 working —
6 7–12 Sep Module 2: Counters, registers Ex 2.3–2.4 progressing —
7 14–17 Sep Finish Project 2 (before Exam I) P2 demo + video Reflection M2
— 18–23 Sep Examination I No new course deadlines —
8 21–26 Sep Module 3 start (post Exam I) Ex 3.1–3.2 underway —
9 28 Sep–3 Oct Module 3: MUX + Project 3 P3 demo + video Reflection M3
10 5–10 Oct Module 4: adders, Double Dabble Ex 4.1–4.3 working —
11 12–16 Oct Project 4 (pre-recess) P4 demo + video Reflection M4
— 17–25 Oct Mid-semester recess No new work required —
12 26–31 Oct Module 5: accumulator, signed, ALU Ex 5.1–5.3 demo —
13 2–7 Nov Module 5 wrap + Capstone kickoff Ex 5.4 + architecture sketch Reflection M5
14 9–14 Nov Capstone build Capstone mid-check demo —
15 16–19 Nov Capstone polish Signed calculator final demo + video Capstone reflection
Exam II 20–28 Nov Final exam — Final exam

Weekly detail

Week 1 — Kickoff and Prerequisites

  • Form teams; receive kits; read policies on this website.
  • Complete Module 0 exercise (LEDs and Basic Circuits).
  • Milestone: live demo of DIP-controlled 7-segment setup.

Week 2 — Module 1 underway

  • Exercises 1.1 and 1.2.
  • Milestone: Boolean / number-representation exercises demonstrated as required in the module.

Week 3 — Counters and reset

  • Exercises 1.3 and 1.4.
  • Milestone: counting and reset logic working on the breadboard.

Week 4 — Project 1 due

  • Build Digital Clock (HH:MM:SS, proper resets, set controls).
  • Milestone: working P1 demo + proof video on CAT-SOOP / Google Classroom.
  • Individual: Reflection M1 (format released end of module).

Week 5 — Module 2 foundations

  • Exercises 2.0–2.2 (debounce, latches, flip-flops).
  • Milestone: debounce + basic memory circuits demoed. Remember: clocked switches must be debounced.

Week 6 — Counters and registers

  • Exercises 2.3–2.4; begin Project 2.
  • Milestone: binary counter / register progress demo.

Week 7 — Project 2 due

  • Finish Up/Down Counter before Examination I week.
  • Milestone: working P2 demo + video.
  • Individual: Reflection M2.

Examination I week (18–23 Sep)

  • No new ES-204 deadlines. Use any spare time to catch up or start Module 3 reading only if you wish.

Week 8 — Module 3 start

  • Exercises 3.1–3.2.
  • Milestone: progress check on Boolean algebra / truth-table exercises.

Week 9 — Project 3 due

  • Exercise 3.3 and Project 3 (custom 7-segment decoder).
  • Milestone: working P3 demo + video.
  • Individual: Reflection M3.

Week 10 — Module 4 exercises

  • Exercises 4.1–4.3 (addition, ripple-carry adder, Double Dabble).
  • Milestone: exercise circuits working.

Week 11 — Project 4 due (before recess)

  • Complete 4-bit Calculator.
  • Milestone: working P4 demo + video.
  • Individual: Reflection M4.

Mid-semester recess (17–25 Oct)

  • No classes; no submissions due during recess.

Week 12 — Module 5 core

  • Exercises 5.1–5.3.
  • Milestone: accumulator / signed / ALU-basics demo.

Week 13 — Module 5 wrap + Capstone start

  • Exercise 5.4 (74181 datasheet exploration).
  • Capstone: paper architecture (input convert → core → output convert → display).
  • Milestone: Ex 5.4 + architecture sketch reviewed by staff.
  • Individual: Reflection M5.

Week 14 — Capstone mid-check

  • Build and test in stages; do not wire everything at once.
  • Milestone: mid-check demo of a substantial partial system.

Week 15 — Capstone due

  • Meet minimum requirements for the Signed Calculator; optional extensions if time allows.
  • Milestone: final demo + video (show positive result, negative result, and subtraction-via-negative-input as required on the modules page).
  • Individual: Capstone reflection.

Examination II — Final exam

  • Individual final exam (format TBD: written + practical).

Textbooks and Readings

There is no single required textbook. Primary materials are on CAT-SOOP: course webpage and modules. Datasheets (e.g. CD4026, 74xx family, 74181, 555) will be linked as needed. Additional readings may be posted on Google Classroom.

Acknowledgements

Instructional content is based on the Center for Creative Learning (CCL) / Madhava Introduction to Digital Electronics course materials at IIT Gandhinagar. Course webpage and policy structure are adapted from prior offerings (including CS 1216 Computer Organization and Systems). The instructor gratefully acknowledges the authors and maintainers of those materials.